This application claims the benefit of Korean Patent Application No. 2001-10843, filed on Mar. 2, 2001, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a method of manufacturing a CMOS TFT.
2. Description of the Related Art
In manufacturing an active display device, it is one of the most important parameters to prevent a leakage current in an off-state of a poly-Si TFT which is used as a switching element. In order to prevent a leakage current, the TFT having a lightly doped drain (LDD) structure or an off-set structure is employed.
There are various methods of manufacturing a conventional TFT having the LDD structure or the off-set structure: a method of forming source and drain regions after undercutting a gate electrode material or gate metal so that a gate electrode may have a smaller width than a photoresist pattern; a method of forming source and drain regions after forming a spacer on a sidewall of a gate electrode; and a method of forming source and drain regions after electrically oxidizing a gate metal to form a gate insulating layer.
FIGS. 1A to 1E illustrate a process of manufacturing a CMOS TFT having an LDD structure according to a conventional art.
As shown in FIG. 1A, a polycrystalline silicon material layer is deposited on an insulating substrate 10. The insulating substrate 10 includes an n-type TFT region 10a on which an n-type TFT will be formed and a p-type TFT region 10b on which a p-type TFT will be formed. The polycrystalline silicon material layer is patterned using a first mask (not shown) to form polycrystalline silicon layers 11a and 11b on the n-type TFT region 10a and the p-type TFT region 10b, respectively. The polycrystalline silicon layers 11a and 11b serve as semiconductor layers (ie., active layer) of the n-type TFT and the p-type TFT, respectively.
A photoresist pattern 12 is formed to cover the polycrystalline silicon layer 11b on the n-type TFT region 10b. A channel doping to the polycrystalline silicon layer 11a is performed to control a threshold voltage using the photoresist pattern 12 as a second mask. Thereafter, the photoresist pattern 12 is removed.
As shown in FIG. 1B, a gate insulating layer 13 is formed over the whole surface of the substrate 10 and covers the polycrystalline silicon layers 11a and 11b. A first metal layer is deposited on the gate insulating layer 13 and patterned using a third mask to form gate electrodes 14a and 14b. 
Thereafter, an n-type low-density impurity is ion-implanted into the semiconductor layers 11a of the n-type TFT region 10a to form LDD regions 15 on both sides of the gate electrode 14a. At this point, the n-type low-density impurity ion-implanted into the p-type TFT region 10b does not affect the p-type TFT because it is offset by a p-type impurity that will be ion-implanted in a subsequent process.
Subsequently, as shown in FIG. 1C, a photoresist pattern 16 is formed on the n-type TFT region 10a. Using the photoresist pattern 16 as a fourth mask, a p-type high-density impurity is ion-implanted into the semiconductor layers 11b of the p-type TFT region 10b to form source and drain regions 17 on both end portions of the polycrystalline silicon layer 11b. Thereafter, the photoresist pattern 16 is removed.
Next, as shown in FIG. 1D, a photoresist pattern 18 is formed to cover the p-type TFT region and the LDD region 15 of the n-type TFT. Using the photoresist pattern 18 as a fifth mask, an n-type high-density impurity is ion-implanted into the polycrystalline silicon layer 11a of the n-type TFT to form source and drain regions 19.
As shown in FIG. 1E, an interlayer insulating layer 20 is formed over the whole surface of the substrate 10. The interlayer insulating layer 20 is patterned using a sixth mask to form contact holes 21a and 21b to expose portions of the source and drain regions 19 and 17.
A second metal layer is deposited over the whole surface of the substrate 10 and patterned using a seventh mask to form source and drain electrodes 22a and 22b. The source and drain electrodes 22a are connected to the source and drain regions 19 through the contacts holes 22a, respectively. The source and drain electrodes 22b are connected to the source and drain regions 17 through the contact holes 22b, respectively. Therefore, the CMOS transistor according to the conventional art is completed.
Meanwhile, if a process is omitted that ion-implants an n-type impurity into the polycrystalline layer 11a of the n-type TFT region 10a, an off-set region is formed instead of the LDD regions 15, so that the CMOS TFT having an off-set structure can be manufactured.
The CMOS TFT having the LDD structure or the off-set structure has an advantage in that a leakage current is lowered, whereupon display characteristics can be improved.
However, in order to manufacture the conventional CMOS TFT having the LDD structure or the off-set structure, many masks (i.e., seven masks) are required. Therefore, a manufacturing process is very complicated, thereby causing low manufacturing yield and high production cost.
Accordingly, it is an object of the present invention provide a method of manufacturing a CMOS TFT having an LDD structure having a simplified manufacturing process.
It is another object of the present invention to provide a method of manufacturing a CMOS TFT having an LDD structure having high manufacturing yield and low production cost.
The foregoing and other objects of the present invention are achieved by providing a method of manufacturing a CMOS TFT, comprising: forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second regions, the first semiconductor layer formed on the first region, the second semiconductor layer formed on the second region; forming sequentially a first insulating layer, a first metal layer and a second insulating layer over the whole surface of the substrate; etching a portion of the first metal layer and a portion of the second insulating layer over the first region of the substrate using a second mask to form a first gate electrode and a first capping layer; forming first spacers on both side wall portions of the first gate electrode and the first capping layer; ion-implanting a first conductive-type high-density impurity into the first semiconductor layer using the first spacers and the first gate electrode as a mask to form first high-density source and drain regions; etching a portion of the first metal layer and a portion of the second insulating layer over the second region of the substrate using a third mask to form a second gate electrode and a second capping layer; and ion-implanting a second conductive-type high density impurity into the second semiconductor layer using the third mask to form second high-density source and drain regions.
The foregoing and other objects of the present invention may also be achieved by providing a method of manufacturing a CMOS TFT, comprising: forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second regions, the first semiconductor layer formed on the first region, the second semiconductor layer formed on the second region; forming sequentially a first insulating layer, a first metal layer and a second insulating layer over the whole surface of the substrate; etching a portion of the first metal layer and a portion of the second insulating layer over the first region of the substrate using a second mask to form a first gate electrode and a first capping layer; ion-implanting a first conductive-type high density impurity into the first semiconductor layers to form first high-density source and drain regions using a third mask; etching a portion of the first metal layer and a portion of the second insulating layer over the second region of the substrate using a fourth mask to form a second gate electrode and a second capping layer; and ion-implanting a second conductive-type high density impurity into the second semiconductor layer using the fourth mask to form second high-density source and drain regions.